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NXP Semiconductors /MIMXRT1062 /ENET /TCR

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Interpret as TCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GTS)GTS 0 (FDEN)FDEN 0 (TFC_PAUSE_0)TFC_PAUSE 0 (RFC_PAUSE)RFC_PAUSE 0 (ADDSEL_0)ADDSEL 0 (ADDINS_0)ADDINS 0 (CRCFWD_0)CRCFWD

CRCFWD=CRCFWD_0, ADDSEL=ADDSEL_0, ADDINS=ADDINS_0, TFC_PAUSE=TFC_PAUSE_0

Description

Transmit Control Register

Fields

GTS

Graceful Transmit Stop
FDEN

Full-Duplex Enable
TFC_PAUSE

Transmit Frame Control Pause

0 (TFC_PAUSE_0): No PAUSE frame transmitted.

1 (TFC_PAUSE_1): The MAC stops transmission of data frames after the current transmission is complete.
RFC_PAUSE

Receive Frame Control Pause
ADDSEL

Source MAC Address Select On Transmit

0 (ADDSEL_0): Node MAC address programmed on PADDR1/2 registers.
ADDINS

Set MAC Address On Transmit

0 (ADDINS_0): The source MAC address is not modified by the MAC.

1 (ADDINS_1): The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
CRCFWD

Forward Frame From Application With CRC

0 (CRCFWD_0): TxBD[TC] controls whether the frame has a CRC from the application.

1 (CRCFWD_1): The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data